Programmable logic devices, or PLDs, are general-purpose circuits that can be programmed by an end user to perform one or more selected functions. Complex PLDs (CPLDs) typically include a number of programmable logic elements and some programmable routing resources. Programmable logic elements have many forms and many names, such as CLBs, logic blocks, logic array blocks, macrocells, logic cells, and functional blocks. Programmable routing (or interconnect) resources also have many forms and many names. This collection of programmable elements and interconnect may be customized by loading “configuration data” into internal configuration memory cells that define how the logic elements and routing resources are configured. The configuration data may be read from memory (e.g., an external memory) or written into the CPLD from an external device. The collective program states of the individual memory cells then determine the function of the CPLD.
Some CPLDs use an array of SRAM known as “shadow” memory to set user functionality. The shadow memory is programmed by moving data from a local non-volatile memory array, such as an EEPROM array, when power is first applied to the CPLD. A primary requirement for transferring data from non-volatile memory into the shadow memory is that the data can be transferred reliably at a voltage lower than the CPLD's minimum supply requirement. Configuring CPLDs before supply voltages are stable is important because CPLDs should be fully configured before circuits with which they communicate are operational, and such circuits are normally enabled after power-supply voltages are stable.
Newer generations of integrated circuits, including CPLDs, use reduced supply voltages. As supply voltages decrease, the margin between the supply voltage required for transferring data to shadow memory and the minimum operational supply voltage also decreases. Unfortunately, reducing this margin increases the probability of a write error from the non-volatile memory array into the shadow memory. Such errors produce incorrect circuit configurations, and thus cannot be tolerated.
Some systems address the problem of data-transfer errors by reading the shadow memory to verify the presence of correct configuration data. This method works well, but is at cross-purposes with a desire to minimize the size of each shadow memory cell. Small memory cells are desirable because they reduce cost and power consumption, but small memory cells may be so sensitive that merely reading their contents can alter the stored bit. This problem is detailed below.
FIG. 1 (prior art) depicts a memory system 100 for use as shadow memory in a CPLD. Memory system 100 includes an array 105 of SRAM cells 110 connected to a memory interface 115. Each SRAM cell 110 is connected to a respective one of word lines WL0–WLN, and all N SRAM cells connect to common complimentary bitline pairs BL and BLb. Each SRAM cell 110 additionally includes a complimentary pair of configuration-bit nodes CBN and CBNb, which connect to corresponding configurable elements (not shown) in the CPLD. The configuration-bit-node pairs collectively define the operation of the various configurable elements of the CPLD.
Memory interface 115 connects to memory array 105 via complimentary bitlines BL and BLb. To write data into memory array 105, a write-enable signal WE on a like-named terminal to memory interface 115 is asserted. A voltage level representative of the bit to be written to one of the SRAM cells 110 is then provided on data input terminal DIN. (Throughout this disclosure, terminals and their respective signals are given identical names; the meaning of the given designation will be clear from the context.) Finally, the SRAM cell 110 to be written is selected by applying a word line signal on the appropriate one of word lines WL0–WLN. For example, to write a bit to the left-most SRAM cell 110 of array 105, write-enable signal WE is asserted, the data bit is presented on terminal DIN, and word line WL0 is asserted. In response to the write-enable signal, memory interface 115 provides a differential version of the input data on bitlines BL and BLb, and the selected SRAM cell 110 latches the data.
FIG. 2 (prior art) details a memory cell 110 of the type included in memory array 105 of FIG. 1. Memory cell 110 includes a pair of cross-coupled inverters 200 and 205 that together form a latch that retains the voltage levels on a pair of complimentary bit nodes 210 and 215. A first access transistor 220 extends between bitline BL and bit node 210, and a second access transistor 225 extends between complimentary bitline BLb and memory bit node 215. To effect a write, the data to be written to memory cell 110 is driven onto complimentary bitlines BL and BLb and word line WL is asserted (e.g., driven high) to render access transistors 220 and 225 conducting. The respective voltages on bitlines BL and BLb are thereby conveyed to cross-coupled inverters 200 and 205. The word line signal WL is then de-asserted, disconnecting the complimentary bitlines from their respective bit nodes 210 and 215. Cross-coupled inverters 200 and 205 thereafter retain a voltage level representative of the written bit.
To read memory cell 110, bitlines BL and BLb are pre-charged to some known level, typically to supply voltage VDD. Word line signal WL is then asserted, so that cross-coupled inverters 200 and 205 drive the latched voltage level onto complimentary bitline BL and BLb. A sense amplifier (not shown) detects the resulting logic level on the bitlines.
Cross-coupled inverters 200 and 205 should be small so that memory cell 110 consumes little power and occupies little real estate. Unfortunately, as inverters 200 and 205 grow smaller, the probability that the pre-charge voltage on the complimentary bitlines will disturb the data stored by inverters 200 and 205 increases. In some cases where shadow RAM is read to verify its contents, it has been found that the process of reading the shadow RAM disturbs one or more bits, and consequently disturbs the performance of the circuit to be instantiated in the associated CPLD. There is therefore a need for a means of providing small, efficient, memories that are less sensitive to read disruptions.